The invention relates to semiconductor wafer testing and more particularly to characterization of semiconductor/oxide interface traps.
As is known in the art, semiconductor wafers often contain material interfaces such as silicon and silicon dioxide. Contaminants and other defects at the oxide silicon interface can cause problems in the manufacture and performance of integrated circuits that are fabricated over the interface. For example, impurities such as metals are often introduced at the oxide layer/semiconductor interface during oxidation processing, plasma deposition or etching or other processing. There is a need to determine the quality of this interface prior to or during the manufacture of semiconductor devices on the wafer.
While prior approaches are known they all rely upon a very indirect measurement of the interface trapped charge. In general the prior approaches use charge-voltage dependence, capacitance-voltage or capacitance-time dependence. In general, they require the fabrication of test structures, such as electrodes on the surface of the wafer or capacitors. This is time-consuming and expensive. Hence a better approach is needed.